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SimTrigHeaderCnv Class Reference

#include <SimTrigHeaderCnv.h>

Inheritance diagram for SimTrigHeaderCnv:
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Collaboration diagram for SimTrigHeaderCnv:
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List of all members.

Public Member Functions

 SimTrigHeaderCnv (ISvcLocator *svc)
virtual ~SimTrigHeaderCnv ()
StatusCode PerToTran (const PerSimTrigHeader &perobj, DayaBay::SimTrigHeader &tranobj)
 Copy data from TObject based class of type TType to DataObject based class of type DOType.
StatusCode TranToPer (const DayaBay::SimTrigHeader &tranobj, PerSimTrigHeader &perobj)
 Copy data from DataObject based class of type DOType to TObject based class of type TType.
StatusCode fillRepRefs (IOpaqueAddress *addr, DataObject *dobj)
StatusCode fillObjRefs (IOpaqueAddress *addr, DataObject *dobj)
PerSimTrigCommandHeaderconvert (const DayaBay::SimTrigCommandHeader &trigCH)
PerSimTrigCommandCollectionconvert (const DayaBay::SimTrigCommandCollection &trigCC)
PerSimTrigCommandconvert (const DayaBay::SimTrigCommand &trigCom)
PerSimRpcTrigCommandconvert (const DayaBay::SimRpcTrigCommand &trigCom)
DayaBay::SimTrigCommandHeaderconvert (const PerSimTrigCommandHeader &PerSimTrigCH)
DayaBay::SimTrigCommandCollectionconvert (const PerSimTrigCommandCollection &PerSimTrigCC)
DayaBay::SimTrigCommandconvert (const PerSimTrigCommand &PerSimTrigCom)
DayaBay::SimRpcTrigCommandconvert (const PerSimRpcTrigCommand &PerSimRpcTrigCom)
PerType & getPerInputObject ()
PerType & getPerOutputObject ()
const RootIOBaseObjectgetBaseInputObject ()
const RootIOBaseObjectgetBaseOutputObject ()
virtual StatusCode PerToTran (const PerType &pobj, TranType &tobj)=0
virtual StatusCode TranToPer (const TranType &tobj, PerType &pobj)=0
virtual StatusCode TranObjectToPerObject (DataObject &dat, const RootOutputAddress &)
virtual StatusCode PerObjectToTranObject (DataObject *&dat)
virtual RootInputStreammakeInputStream (const RootInputAddress &ria)
virtual RootOutputStreammakeOutputStream (const RootOutputAddress &ria)
virtual long repSvcType () const
virtual StatusCode initialize ()
virtual StatusCode finalize ()
virtual StatusCode createObj (IOpaqueAddress *addr, DataObject *&dat)
virtual StatusCode createRep (DataObject *pObject, IOpaqueAddress *&refpAddress)
int commit (const RootOutputAddress &roa)
RootIOBaseCnvotherConverter (int clID)

Static Public Member Functions

static const CLID & classID ()
static unsigned char storageType ()
static const InterfaceID & interfaceID ()

Protected Attributes

std::string m_perclassName
PerType * m_perInObj
PerType * m_perOutObj
IRootIOSvcm_rioSvc
IConversionSvc * m_cnvSvc
RootInputStreamm_ris

Detailed Description

Definition at line 27 of file SimTrigHeaderCnv.h.


Constructor & Destructor Documentation

SimTrigHeaderCnv::SimTrigHeaderCnv ( ISvcLocator *  svc)

Definition at line 16 of file SimTrigHeaderCnv.cc.

    : RootIOTypedCnv<PerSimTrigHeader,SimTrigHeader>("PerSimTrigHeader",
                                                classID(),svc)
{
}
SimTrigHeaderCnv::~SimTrigHeaderCnv ( ) [virtual]

Definition at line 22 of file SimTrigHeaderCnv.cc.

{
}

Member Function Documentation

static const CLID& SimTrigHeaderCnv::classID ( ) [inline, static]

Definition at line 31 of file SimTrigHeaderCnv.h.

                               {
    return DayaBay::CLID_SimTrigHeader;
  }
StatusCode SimTrigHeaderCnv::PerToTran ( const PerSimTrigHeader perobj,
DayaBay::SimTrigHeader tranobj 
)

Copy data from TObject based class of type TType to DataObject based class of type DOType.

Definition at line 26 of file SimTrigHeaderCnv.cc.

{
  MsgStream log(msgSvc(), "SimTrigHeaderCnv::PerToTran");

  StatusCode sc = HeaderObjectCnv::toTran(perobj,tranobj);
  if (sc.isFailure()) return sc;
  DayaBay::SimTrigCommandHeader *tch = convert( *(perobj.commandHeader) );
  tch->setHeader(&tranobj);
  tranobj.setCommandHeader( tch );

  return StatusCode::SUCCESS;
}
StatusCode SimTrigHeaderCnv::TranToPer ( const DayaBay::SimTrigHeader tranobj,
PerSimTrigHeader perobj 
)

Copy data from DataObject based class of type DOType to TObject based class of type TType.

Definition at line 40 of file SimTrigHeaderCnv.cc.

{
  MsgStream log(msgSvc(), "SimTrigHeaderCnv::TranToPer");

  StatusCode sc = HeaderObjectCnv::toPer(tranobj,perobj);
  if (sc.isFailure()) return sc;

  delete perobj.commandHeader;

  if( tranobj.commandHeader() != 0 ) {
    perobj.commandHeader = convert( *(tranobj.commandHeader()) );
  }
  return StatusCode::SUCCESS;
}
StatusCode SimTrigHeaderCnv::fillRepRefs ( IOpaqueAddress *  addr,
DataObject *  dobj 
) [virtual]

Reimplemented from RootIOTypedCnv< PerSimTrigHeader, DayaBay::SimTrigHeader >.

Definition at line 56 of file SimTrigHeaderCnv.cc.

{
    MsgStream log(msgSvc(), "SimTrigHeaderCnv::fillRepRefs");
    SimTrigHeader* th = dynamic_cast<SimTrigHeader*>(dobj);

    log << MSG::DEBUG
        << "Saving links to " << th->inputHeaders().size()
        << " input headers" << endreq;

    StatusCode sc = HeaderObjectCnv::fillPer(m_rioSvc,*th,*m_perOutObj);
    if (sc.isFailure()) {
        log << MSG::ERROR << "Failed to fill HeaderObject part" << endreq;
        return sc;
    }

    // ... fill SimTrigHeader part...
    return sc;
}
StatusCode SimTrigHeaderCnv::fillObjRefs ( IOpaqueAddress *  addr,
DataObject *  dobj 
) [virtual]

Reimplemented from RootIOTypedCnv< PerSimTrigHeader, DayaBay::SimTrigHeader >.

Definition at line 75 of file SimTrigHeaderCnv.cc.

{
    MsgStream log(msgSvc(), "SimTrigHeaderCnv::fillObjRefs");
    HeaderObject* hobj = dynamic_cast<HeaderObject*>(dobj);
    StatusCode sc = HeaderObjectCnv::fillTran(m_rioSvc,*m_perInObj,*hobj);
    if (sc.isFailure()) {
        log << MSG::ERROR << "Failed to fill HeaderObject part" << endreq;
        return sc;
    }

    log << MSG::DEBUG
        << "Restored links to " << hobj->inputHeaders().size()
        << " input headers" << endreq;

    // ... fill SimTrigHeader part...
    return sc;
}
PerSimTrigCommandHeader * SimTrigHeaderCnv::convert ( const DayaBay::SimTrigCommandHeader trigCH)

Definition at line 95 of file SimTrigHeaderCnv.cc.

{
  MsgStream log(msgSvc(), "SimTrigHeaderCnv::convet Header");
  PerSimTrigCommandHeader::PerComVector outCollVec;
  SimTrigCommandHeader::detCollMap inCollVec;
  inCollVec = trigCH.collections();
  SimTrigCommandHeader::detCollMap::iterator it;
  log << MSG::DEBUG  <<"** Converting"
            << inCollVec.size()
            << " SimTrigCommandCollections."
            << endreq;
  for(it = inCollVec.begin(); it != inCollVec.end(); ++it){
    outCollVec.push_back( convert( *(it->second) ) );
  }
  return new PerSimTrigCommandHeader(outCollVec);
}
PerSimTrigCommandCollection * SimTrigHeaderCnv::convert ( const DayaBay::SimTrigCommandCollection trigCC)

Definition at line 112 of file SimTrigHeaderCnv.cc.

{
  PerSimTrigCommandCollection::CommandVectors out_commands;
  SimTrigCommandCollection::CommandContainer in_commands = trigCC.commands();
  SimTrigCommandCollection::CommandContainer::iterator it;
  for(it = in_commands.begin(); it != in_commands.end(); ++it){
    if (trigCC.detector().isRPC())
        out_commands.push_back( convert(*static_cast<DayaBay::SimRpcTrigCommand*>(*it)) );
    else
        out_commands.push_back(convert(**it));
  }
  short int det = (trigCC.detector()).siteDetPackedData();
  return new PerSimTrigCommandCollection(det,out_commands);
}
PerSimTrigCommand * SimTrigHeaderCnv::convert ( const DayaBay::SimTrigCommand trigCom)

Definition at line 127 of file SimTrigHeaderCnv.cc.

                                                                                {
  const int cc = trigCom.clockCycle();
  const int type = trigCom.type();
  short int det = (trigCom.detector()).siteDetPackedData();
  const int nh  = trigCom.nhit();
  const int esA = trigCom.esumAdc();
  const int esC = trigCom.esumComp();
  return new PerSimTrigCommand(cc,type,det,nh,esA,esC);
}
PerSimRpcTrigCommand * SimTrigHeaderCnv::convert ( const DayaBay::SimRpcTrigCommand trigCom)

Definition at line 137 of file SimTrigHeaderCnv.cc.

                                                                               {
    const int cc = trigCom.clockCycle();
    const int type = trigCom.type();
    short int det = (trigCom.detector()).siteDetPackedData();

    const SimRpcTrigCommand::TrigChannels& inTrigs = trigCom.inTriggers();
    const SimRpcTrigCommand::TrigChannels& outTrigs = trigCom.outTriggers();

    PerSimRpcTrigCommand::TriggerMap out_inTrigs;
    PerSimRpcTrigCommand::TriggerMap out_outTrigs;

    SimRpcTrigCommand::TrigChannels::const_iterator inIt, inDone = inTrigs.end();
    for (inIt = inTrigs.begin(); inIt != inDone; inIt++) {
        out_inTrigs[inIt->first.fullPackedData()] = inIt->second;
    }

    SimRpcTrigCommand::TrigChannels::const_iterator outIt, outDone = outTrigs.end();
    for (outIt = outTrigs.begin(); outIt != outDone; outIt++) {
        out_outTrigs[outIt->first.fullPackedData()] = outIt->second;
    }

    MsgStream log(msgSvc(), "SimTrigHeaderCnv::convet SimRpcTrigCommand");
    log<<MSG::DEBUG<<"Converting command :" << trigCom <<endreq;
    log<<MSG::VERBOSE<<"cc = " << cc << "\ntype = " << type << "\ndet = " << det <<endreq;

    return new PerSimRpcTrigCommand(cc, type, det, out_inTrigs, out_outTrigs);
}
DayaBay::SimTrigCommandHeader * SimTrigHeaderCnv::convert ( const PerSimTrigCommandHeader PerSimTrigCH)

Definition at line 165 of file SimTrigHeaderCnv.cc.

                                                                                                 {
  // set header pointer after return
  SimTrigCommandHeader *out_header = new SimTrigCommandHeader();

  PerSimTrigCommandHeader::PerComVector in_collection = PerSimTrigCH.commandCollections;
  PerSimTrigCommandHeader::PerComVector::iterator it;
  SimTrigCommandHeader::detCollMap out_collection;

  for(it=in_collection.begin();it!=in_collection.end();++it){
    SimTrigCommandCollection *out_cc = convert(**it);
    out_header->addCollection(out_cc);
    //out_cc->setHeader(out_header);
    //out_collection[out_cc->detector()]=out_cc;
  }
  return out_header;
}
DayaBay::SimTrigCommandCollection * SimTrigHeaderCnv::convert ( const PerSimTrigCommandCollection PerSimTrigCC)

Definition at line 182 of file SimTrigHeaderCnv.cc.

                                                                                                         {
  Detector det(PerSimTrigCC.detector);
  SimTrigCommandCollection::CommandContainer out_commands;
  PerSimTrigCommandCollection::CommandVectors in_commands = PerSimTrigCC.commands;
  PerSimTrigCommandCollection::CommandVectors::iterator it;

  for(it = in_commands.begin(); it != in_commands.end(); ++it)
  {
    if (det.isRPC())
        out_commands.push_back( convert(*static_cast<PerSimRpcTrigCommand*>(*it)) );
    else
        out_commands.push_back( convert(**it) );
  }

  return new SimTrigCommandCollection(det,out_commands);
}
DayaBay::SimTrigCommand * SimTrigHeaderCnv::convert ( const PerSimTrigCommand PerSimTrigCom)

Definition at line 199 of file SimTrigHeaderCnv.cc.

                                                                                      {
  MsgStream log(msgSvc(), "SimTrigHeaderCnv::convet PerSimTrigCommand");
  Detector det(PerSimTrigCom.detector);
  Trigger::TriggerType_t ttype=(Trigger::TriggerType_t)PerSimTrigCom.type;
  SimTrigCommand *out_command = new SimTrigCommand(det,ttype,PerSimTrigCom.clockCycle,PerSimTrigCom.nhit,PerSimTrigCom.esumAdc,PerSimTrigCom.esumComp);
  log << MSG::VERBOSE  <<"** Created"
      << *out_command << endreq;
  return out_command;
}
SimRpcTrigCommand * SimTrigHeaderCnv::convert ( const PerSimRpcTrigCommand PerSimRpcTrigCom)

Definition at line 209 of file SimTrigHeaderCnv.cc.

                                                                               {
    MsgStream log(msgSvc(), "SimTrigHeaderCnv::convet PerSimRpcTrigCommand");
    Detector det(trigCom.detector);
    Trigger::TriggerType_t ttype=(Trigger::TriggerType_t)trigCom.type;

    const PerSimRpcTrigCommand::TriggerMap& inTrigs = trigCom.inTriggers;
    const PerSimRpcTrigCommand::TriggerMap& outTrigs = trigCom.outTriggers;

    SimRpcTrigCommand::TrigChannels out_inTrigs;
    SimRpcTrigCommand::TrigChannels out_outTrigs;

    PerSimRpcTrigCommand::TriggerMap::const_iterator inIt, inDone = inTrigs.end();
    for (inIt = inTrigs.begin(); inIt != inDone; inIt++) {
        out_inTrigs[FecChannelId(inIt->first)] = (Trigger::TriggerType_t) inIt->second;
    }

    PerSimRpcTrigCommand::TriggerMap::const_iterator outIt, outDone = outTrigs.end();
    for (outIt = outTrigs.begin(); outIt != outDone; outIt++) {
        out_outTrigs[FecChannelId(outIt->first)] = (Trigger::TriggerType_t) outIt->second;
    }

    SimRpcTrigCommand *out_command = new SimRpcTrigCommand(det,ttype,trigCom.clockCycle);
    out_command->setInTriggers(out_inTrigs);
    out_command->setOutTriggers(out_outTrigs);

    log << MSG::VERBOSE  <<"** Created"
      << *out_command << endreq;

    return out_command;
}
PerType & RootIOTypedCnv< class, class >::getPerInputObject ( ) [inherited]
PerType & RootIOTypedCnv< class, class >::getPerOutputObject ( ) [inherited]
const RootIOBaseObject * RootIOTypedCnv< class, class >::getBaseInputObject ( ) [virtual, inherited]

Implements RootIOBaseCnv.

const RootIOBaseObject * RootIOTypedCnv< class, class >::getBaseOutputObject ( ) [virtual, inherited]

Implements RootIOBaseCnv.

virtual StatusCode RootIOTypedCnv< class, class >::PerToTran ( const PerType &  pobj,
TranType &  tobj 
) [pure virtual, inherited]
virtual StatusCode RootIOTypedCnv< class, class >::TranToPer ( const TranType &  tobj,
PerType &  pobj 
) [pure virtual, inherited]
virtual StatusCode RootIOTypedCnv< class, class >::TranObjectToPerObject ( DataObject &  dat,
const RootOutputAddress  
) [virtual, inherited]

Implements RootIOBaseCnv.

virtual StatusCode RootIOTypedCnv< class, class >::PerObjectToTranObject ( DataObject *&  dat) [virtual, inherited]

Implements RootIOBaseCnv.

virtual RootInputStream * RootIOTypedCnv< class, class >::makeInputStream ( const RootInputAddress ria) [virtual, inherited]

Implements RootIOBaseCnv.

virtual RootOutputStream * RootIOTypedCnv< class, class >::makeOutputStream ( const RootOutputAddress ria) [virtual, inherited]

Implements RootIOBaseCnv.

virtual long RootIOTypedCnv< class, class >::repSvcType ( ) const [virtual, inherited]

Reimplemented from RootIOBaseCnv.

virtual StatusCode RootIOTypedCnv< class, class >::initialize ( ) [virtual, inherited]

Reimplemented from RootIOBaseCnv.

virtual StatusCode RootIOTypedCnv< class, class >::finalize ( ) [virtual, inherited]

Reimplemented from RootIOBaseCnv.

virtual StatusCode RootIOTypedCnv< class, class >::createObj ( IOpaqueAddress *  addr,
DataObject *&  dat 
) [virtual, inherited]

Reimplemented from RootIOBaseCnv.

virtual StatusCode RootIOTypedCnv< class, class >::createRep ( DataObject *  pObject,
IOpaqueAddress *&  refpAddress 
) [virtual, inherited]

Reimplemented from RootIOBaseCnv.

int RootIOTypedCnv< class, class >::commit ( const RootOutputAddress roa) [inherited]

Reimplemented from RootIOBaseCnv.

RootIOBaseCnv * RootIOTypedCnv< class, class >::otherConverter ( int  clID) [inherited]

Reimplemented from RootIOBaseCnv.

static unsigned char RootIOTypedCnv< class, class >::storageType ( ) [static, inherited]

Reimplemented from RootIOBaseCnv.

static const InterfaceID & RootIOTypedCnv< class, class >::interfaceID ( ) [static, inherited]

Reimplemented from RootIOBaseCnv.


Member Data Documentation

std::string RootIOTypedCnv< class, class >::m_perclassName [protected, inherited]
PerType * RootIOTypedCnv< class, class >::m_perInObj [protected, inherited]
PerType * RootIOTypedCnv< class, class >::m_perOutObj [protected, inherited]
IRootIOSvc * RootIOTypedCnv< class, class >::m_rioSvc [protected, inherited]

Reimplemented from RootIOBaseCnv.

IConversionSvc * RootIOTypedCnv< class, class >::m_cnvSvc [protected, inherited]

Reimplemented from RootIOBaseCnv.

RootInputStream * RootIOTypedCnv< class, class >::m_ris [protected, inherited]

Reimplemented from RootIOBaseCnv.


The documentation for this class was generated from the following files:
| Classes | Job Modules | Data Objects | Services | Algorithms | Tools | Packages | Directories | Tracs |

Generated on Fri May 16 2014 10:05:22 for PerSimTrigEvent by doxygen 1.7.4